In accordance to the scaling technology, the total delay of the logic circuit depends on ______
A. The capacitor to be charged
B. The voltage through which capacitance must be charged
C. Available current
D. All of the above
The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.
A. Waveform Editor
B. Waveform Estimator
C. Waveform Simulator
D. Waveform Evaluator
Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?
_________ is the fundamental architecture block or element of a target PLD.
A. System Partitioning
B. Pre-layout Simulation
C. Logic cell
D. Post-layout Simulation
In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?
B. Placement & Routing
Among the VHDL features, which language statements are executed at the same time in parallel flow?