In logic synthesis, ________ is an EDIF that gives the description of logic cells & their interconnections.
The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.
A. Waveform Editor
B. Waveform Estimator
C. Waveform Simulator
D. Waveform Evaluator
Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?
_________ is the fundamental architecture block or element of a target PLD.
A. System Partitioning
B. Pre-layout Simulation
C. Logic cell
D. Post-layout Simulation
In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?
B. Placement & Routing
Among the VHDL features, which language statements are executed at the same time in parallel flow?