In SM chart for UART transmitter, which state/s indicate/s the waiting of sequential machine for the rising edge of bit clock and the consequent clearing of low order bit of TSR in order to transmit logic '0' for one bit time?

The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.

A. Waveform Editor

B. Waveform Estimator

C. Waveform Simulator

D. Waveform Evaluator

Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?

A. Simulation

B. Optimization

C. Synthesis

D. Verification

_________ is the fundamental architecture block or element of a target PLD.

A. System Partitioning

B. Pre-layout Simulation

C. Logic cell

D. Post-layout Simulation

In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?

A. Floorplanning

B. Placement & Routing

C. Testing

D. Extraction

Among the VHDL features, which language statements are executed at the same time in parallel flow?

A. Concurrent

B. Sequential

C. Net-list

D. Test-bench