The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.

Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?

A. Simulation

B. Optimization

C. Synthesis

D. Verification

_________ is the fundamental architecture block or element of a target PLD.

A. System Partitioning

B. Pre-layout Simulation

C. Logic cell

D. Post-layout Simulation

In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?

A. Floorplanning

B. Placement & Routing

C. Testing

D. Extraction

Among the VHDL features, which language statements are executed at the same time in parallel flow?

A. Concurrent

B. Sequential

C. Net-list

D. Test-bench

In Net-list language, the net-list is generated _______synthesizing VHDL code.

A. Before

B. At the time of (during)

C. After

D. None of the above