Which among the following is/are responsible for the occurrence of clock skew by introducing delays from different paths of clock generator to various circuits?
A. Different length of wires
B. Gates on the paths
C. Gating of clock to control the loading of registers
D. All of the above
Related Questions on Digital Electronics Test Questions
A. PMOS
B. NMOS
C. CMOS
D. All of the above
Which type of output current flows towards or into the output terminal in a logic circuit?
A. Sourcing current
B. Sinking current
C. Both a and b
D. None of the above
A. 6 inputs
B. 6 outputs
C. 12 nodes
D. 12 branches
A. Output will always be equal to input
B. Output will always be high
C. Output will always be low
D. Output will always be same
How is the relation specified between input and output in logic circuits?
A. Switching equations
B. Truth-table
C. Logic diagram
D. All of the above