Which level of routing resources are supposed to be the dedicated lines allowing output of each tile to connect directly to every input of eight surrounding tiles?

The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.

A. Waveform Editor

B. Waveform Estimator

C. Waveform Simulator

D. Waveform Evaluator

Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?

A. Simulation

B. Optimization

C. Synthesis

D. Verification

_________ is the fundamental architecture block or element of a target PLD.

A. System Partitioning

B. Pre-layout Simulation

C. Logic cell

D. Post-layout Simulation

In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?

A. Floorplanning

B. Placement & Routing

C. Testing

D. Extraction

Among the VHDL features, which language statements are executed at the same time in parallel flow?

A. Concurrent

B. Sequential

C. Net-list

D. Test-bench